The present invention relates to a demodulation circuit and, more particularly, to a pulse counter type demodulation circuit.
Recently, pulse counter demodulation circuits are used frequently since they can be integrated and they do not need adjustment.
FIG. 1 is a block diagram of a typical conventional pulse counter type demodulation circuit.
Referring to FIG. 1, a modulated signal applied to an input terminal 1 is converted into a pulse signal by a Schmitt trigger circuit 2. An output pulse signal from the Schmitt trigger circuit 2 is input to a monostable multivibrator 31 and converted into a pulse position modulated (PPM) signal comprising pulses having a predetermined width. An output PPM signal from the monostable multivibrator 31 is input to a low-pass filter 4 to remove its high-frequency components. An output signal from the low-pass filter 4 is compared with a reference voltage VR as a threshold level by a comparator 7. Signals higher and lower than the reference voltage are respectively assigned to two voltage levels and output to an output terminal 8 as demodulated signals.
In the pulse counter type demodulation circuit shown in FIG. 1, the voltage of the demodulated signal appearing at the output terminal 8 is defined by the pulse width and amplitude of the PPM signal obtained by the monostable multivibrator 31. Therefore, when a source voltage +V applied to the monostable multivibrator 31 varies, or when the values of the circuit elements of the monostable multivibrator 31 are changed by a change in temperature or the like and accordingly the pulse width or the pulse amplitude of the PPM signal varies, the output voltage from the monostable multivibrator 31 and, accordingly, the output voltage from the low-pass filter 4 varies. Since the reference voltage VR supplied to the comparator 7 does not vary, the comparison result of the comparator 7 directly reflects the influence of the above variation. Therefore, when a digital signal such as an FSK (frequency shift keying) signal and a binary FM signal is to be demodulated, a bit error rate (BER) in the demodulated signal becomes higher.
U.S. Pat. No. 4,389,621 discloses a phase-locked loop (PLL) circuit which uses a voltage controlled oscillator for suppressing the unstable operation of a digital circuit caused by the variation in temperature or source voltage. However, correction using the PLL circuit is performed only when the PPL circuit is in the locking state and when the pulse amplitude of a 50% duty cycle output from an S-R flip-flop varies, and an unstable operation caused by a variation in pulse width is not corrected. Furthermore, since the PLL circuit has a loop arrangement, it is not suitable for demodulation of high-speed data and cannot demodulate input signals supplied in a burst manner.